The present invention relates generally to electrostatic discharge (“ESD”) protection, and more particularly, to an ESD clamp circuit for a mixed-voltage input/output (“I/O”) interface.
Electrostatic discharge (ESD) is a phenomenon that poses a deadly threat to the integrated circuit (IC). A typical ESD event—for instance, when you rub your feet on a carpet and touch a conductive object—can easily destroy a semiconductor device. Strictly speaking, ESD is a rapid discharge event that transfers a finite amount of charge between two bodies at different potentials. The damage caused on an IC depends on the current densities and voltage gradients developed during the event.
ESD damage has become the main reliability issue for complementary metal-oxide-semiconductor (“CMOS”) integrated circuit (“IC”) products fabricated in nanoscale CMOS processes. In a nanoscale IC, the thickness of gate oxide films is reduced as the geometry of the IC is reduced, resulting in a decrease in the operating voltage required for internal circuits and in turn, the power consumption.
In an electronic system having multiple sub-systems, such as in a computer system, there are generally a plurality of power supplies providing different power levels. The sub-systems, such as ICs and chips in the system often require different power supply voltages. Therefore, to be compatible with different power supply voltages, the operating voltage at the input/output (I/O) interfaces of an IC may be greater than the operating voltage of the IC. For example, in an IC fabricated by a 0.18-μm CMOS process, the internal circuits operate at a power supply voltage of approximately 1.8V (volts), while the I/O devices may operate at a power supply voltage of approximately 3.3V, or transmit or receive signals having a voltage level of 3.3V in a mixed-voltage system. To avoid an excessive electrical field due to an excessive voltage applied across nodes of the I/O device, which may cause degradation or breakdown of the gate oxides, in a conventional method, I/O devices are fabricated with a relatively thick gate oxide so as to sustain the excessive voltage. However, such a conventional method decreases the product yield and requires an additional mask in the manufacturing process, resulting in an increase in the product cost.
A feasible way of solution is required to maintain the electrical property and device geometry in nanoscale CMOS ICs without compromising the product yield and throughput. Such a solution may be implemented in circuitry. It is therefore desirable to have an ESD clamp circuit that is able to quickly respond to an ESD event to protect an internal circuit without affecting the operation of the internal circuit to during a normal condition.